philips semiconductors linear products product specification mc145406 eia-232-d/v.28 driver/receiver 467 august 31, 1994 853-1430 13721 description the mc145406 is a silicon-gate cmos ic that combines 3 drivers and 3 receivers to fulfill the electrical specifications of standards eia-232-d and ccitt v .28. the drivers feature true ttl input compatibility , slew-rate limited output, 300 w power-off source impedance, and output typically switching to within 25% of the supply rails. the receivers can handle up to + 25v while presenting 3 to 7k w impedance. hysteresis in the receiver aids reception of noisy signals. by combining both drivers and receivers in a single cmos chip, the mc145406 provides efficient, low-power solutions for eia-232-d and v.28 applications. applications ? modem interface ? v oice/data telephone interface ? lap-top computers ? uart interface features ? drivers ? + 5 to + 12v supply range ? 300 w power-off source impedance ? output current limiting ? ttl compatible pin configuration v dd rx 1 v cc do1 di1 do2 di2 do3 gnd d and n packages 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 tx 1 v ss rx 2 tx 2 rx 3 tx 3 di3 note: d = driver r = receiver r d r d r d ? maximum slew rate = 30v/ m s ? receivers ? + 25v input voltage range over the full supply range ? 3 to 7k w input impedance ? hysteresis on input switchpoint ? general ? v ery low supply currents for long battery life ? operation is independent of power supply sequencing ordering information description temperature range order code dwg # 16-pin plastic dual in-line (dip) package 0 to +70 c mc145406n 0406c 16-pin small outline large (sol) package 0 to +70 c mc145406d 0171b absolute maximum ratings symbol parameter rating units v cc supply voltage -0.5 to +6.0 v v dd supply voltage -0.5 to +13.5 v v ss supply voltage +0.5 to -13.5 v v ir input voltage range rx 1-3 inputs di 1-3 inputs (v ss - 15) to (v dd + 15) -0.5 to (v cc + 0.5) v dc current per pin + 100 ma p d power dissipation (package) 1.0 w t a operating temperature range 0 to +70 c t stg storage temperature range -65 to +150 c q ja thermal impedance n package d package 80 105 c/w note: this device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields; however , it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. for proper operation, it is recommended that the voltages at the di and do pins be constrained to the range gnd < v di < v dd and gnd < v do < v cc . also, the voltage at the rx pin should be constrained to + 25v , and tx should be constrained to v ss < v tx1-3 < v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., gnd or v cc for di, and v ss or v dd for rx).
philips semiconductors linear products product specification mc145406 eia-232-d/v.28 driver/receiver august 31, 1994 468 block diagram receiver do di 1.4v level shift driver hysteresis 300 15k 5.4k rx tx v cc v ss v cc v dd v ss v cc 1.0v 1.8v + + pin # symbol pin description 1 v dd positive power supply . the most positive power supply pin, which is typically 5 to 12 volts. 8 v ss negative power supply. the most negative power supply pin, which is typically -5 to -12 volts. 16 v cc digital power supply . the digital supply pin, which is connected to the logic power supply (maximum +5.5v). 9 gnd ground. ground return pin is typically connected to the signal ground pin of the eia-232-d connector (pin 7) as well as to the logic power supply ground. 2, 4, 6 rx 1 , rx 2 , rx 3 receive data input. these are the eia-232-d receive signal inputs whose voltages can range from +25 to -25v. a voltage between +3 and +25 is decoded as a space and causes the corresponding do pin to swing to ground (0v); a voltage between -3 and -25v is decoded as a mark and causes the do pin to swing up to v cc . the actual turn-on input switchpoint is typically biased at 1.8v above ground, and includes 800mv of hysteresis for noise rejection. the nominal input impedance is 5k w . an open or grounded input pin is interpreted as a mark, forcing the do pin to v cc . 11, 13, 15 do1, do2, do3 data output. these are the receiver digital output pins, which swing from v cc to gnd. a space on the rx pin causes do to produce a logic zero; a mark produces a logic one. each output pin is capable of driving one lsttl input load. 10, 12, 14 di1, di2, di3 data input. these are the high-impedance digital input pins to the drivers. ttl compatibility is accomplished by biasing the input switchpoint at 1.4v above ground. however , 5v cmos compatibility is maintained as well. input voltage levels on these pins must be between v cc and gnd. 3, 5, 7 tx1, tx2, tx3 transmit data output. these are the eia-232-d transmit signal output pins, which swing toward v dd and v ss . a logic one at a di input causes the corresponding tx output to swing toward v ss . a logic zero causes the output to swing toward v dd (the output voltages will be slightly less than v dd or v ss depending upon the output load). output slew rates are limited to a maximum of 30v/ m s. when the mc145406 is of f (v dd = v ss = v cc = gnd), the minimum output impedance is 300 w .
philips semiconductors linear products product specification mc145406 eia-232-d/v.28 driver/receiver august 31, 1994 469 absolute maximum ratings symbol parameter rating units v cc supply voltage -0.5 to +6.0 v v dd supply voltage -0.5 to +13.5 v v ss supply voltage +0.5 to -13.5 v v ir input voltage range rx 1-3 inputs di 1-3 inputs (v ss - 15) to (v dd + 15) -0.5 to (v cc + 0.5) v dc current per pin + 100 ma p d power dissipation (package) 1.0 w t a operating temperature range 0 to +70 c t stg storage temperature range -65 to +150 c q ja thermal impedance n package d package 80 105 c/w note: this device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields; however , it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. for proper operation, it is recommended that the voltages at the di and do pins be constrained to the range gnd < v di < v dd and gnd < v do < v cc . also, the voltage at the rx pin should be constrained to + 25v , and tx should be constrained to v ss < v tx1-3 < v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., gnd or v cc for di, and v ss or v dd for rx). dc electrical characteristics typical values are at t a = 0 to 70 c; gnd = 0v, unless otherwise specified. symbol parameter test conditions limits units symbol parameter test conditions min typ max units dc supply voltage v dd 4.5 5 to 12 13.2 v v ss -4.5 -5 to -12 -13.2 v v cc 4.5 5.0 5.5 v quiescent supply current (outputs unloaded, inputs low) i dd v dd = +12v 20 400 m a i ss v ss = -12v 280 600 m a i cc v cc = +5v 260 450 m a receiver electrical characteristics typical values are at t a = 0 to 70 c; gnd = 0v; v dd = +5 to +12v; v ss = -5 to -12v; v cc = +5v + 5%, unless otherwise specified. symbol parameter test conditions limits units symbol parameter test conditions min typ max units v on input turn-on threshold rx 1-3 v do1-3 = v ol , v cc = 5.0v + 5% 1.35 1.80 2.35 v v off input turn-off threshold rx 1-3 v do1-3 = v oh , v cc = 5.0v + 5% 0.75 1.00 1.25 v v on -v off input threshold hysteresis rx 1-3 v cc = 5.0v + 5% 0.6 0.8 v r in input resistance rx 1-3 (v ss -15v) < v rx1-3 < (v dd +15v) 3.0 5.0 7.0 k w v oh high level output voltage do 1-3 i oh = -20 m a, v cc = +5.0v 4.9 5.0 v v rx1-3 = -3v to (v ss -15v) 1 i oh = -1ma, v cc = +5.0v 3.8 4.4 v v ol low level output voltage do 1-3 v rx1-3 = +3v to (v dd +15v) 1 i ol = +20 m a, v cc = +5.0v 0.005 0.1 v v ol low level output voltage do 1-3 v rx1-3 = +3v to (v dd +15v) 1 i ol = +2ma, v cc = +5.0v 0.15 0.5 v v rx1-3 = +3v to (v dd +15v) 1 i ol = +4ma, v cc = +5.0v 0.3 0.7 note: 1. this is the range of input voltages as specified by eia-232-d to cause a receiver to be in the high or low logic state.
philips semiconductors linear products product specification mc145406 eia-232-d/v.28 driver/receiver august 31, 1994 470 driver electrical characteristics typical values are at t a = 0 to 70 c; gnd = 0v; v cc = +5v + 5%, unless otherwise specified. symbol parameter test conditions limits units symbol parameter test conditions min typ max units v il digital input voltage di 1-3 logic 0 0.8 v v ih digital input voltage di 1-3 logic 1 2.0 v i in input current di 1-3 v di1-3 = v cc + 1.0 m a v oh output high voltage tx 1-3 v di1-3 = logic 0, r l = 3.0k w v dd = +5.0v, v ss = -5.0v 3.5 4.1 v v oh output high voltage tx 1-3 v di1-3 = logic 0, r l = 3.0k w v dd = +6.0v, v ss = -6.0v 4.3 5.0 v v di1-3 = logic 0, r l = 3.0k w v dd = +12.0v, v ss = -12.0v 9.2 10.4 v ol output low voltage 1 tx 1-3 v di1-3 = logic 0, r l = 3.0k w v dd = +5.0v, v ss = -5.0v -4.0 -4.3 v v ol output low voltage 1 tx 1-3 v di1-3 = logic 0, r l = 3.0k w v dd = +6.0v, v ss = -6.0v -4.5 -5.2 v v di1-3 = logic 0, r l = 3.0k w v dd = +12.0v, v ss = -12.0v -10.0 -10.3 off source resistance tx 1-3 figure 1 v dd =v ss =gnd=0v, v tx1-3 = + 2.0v 300 w i sc output short-circuit current tx 1-3 tx 1-3 shorted to gnd 2 + 22 + 60 ma v dd = +12.0v, v ss = -12.0v tx 1-3 shorted to + 15.0v 3 + 60 + 100 ma note: 1. the voltage specifications are in terms of absolute values. 2. specification is for one tx output pin to be shorted at a time. should all three driver outputs be shorted simultaneously , device power dis- sipation limits will be exceeded. 3. this condition could exceed package limitations. switching characteristics typical values are at t a = 0 to 70 c; v cc = +5v + 5%, unless otherwise specified. (see figures 2 and 3) symbol parameter test conditions limits units symbol parameter test conditions min typ max units drivers t plh propagation delay time tx 1-3 low-to-high r l = 3k w , c l = 50pf 300 500 ns t phl propagation delay time tx 1-3 high-to-low r l = 3k w , c l = 50pf 300 500 ns sr output slew rate tx 1-3 (minimum load) r l = 7k w , c l = 0pf, v dd = 6 to 12.0v, v ss = -6 to -12v + 6 + 30 v/ m s sr output slew rate tx 1-3 (maximum load) r l = 3k w , c l = 2500pf, v dd = 12v, v ss = -12v + 3.0 v/ m s receivers (c l = 50pf) t plh propagation delay time do 1-3 low-to-high 150 425 ns t phl propagation delay time do 1-3 high-to-low 150 425 ns t r output rise time do 1-3 120 400 ns t f output fall time do 1-3 40 100 ns
philips semiconductors linear products product specification mc145406 eia-232-d/v.28 driver/receiver august 31, 1994 471 v dd v cc 1 14 12 10 8 9 7 5 3 16 v ss di 1 di 2 di 3 tx 1 tx 2 tx 3 v in = + 2v r out i = v in figure 1. power-off source resistance (drivers) drivers receivers 3v 0v +3v 0v 50% 90% 10% 50% 90% 50% 10% di 1-3 tx 1-3 v oh v ol t plh t phl t f t f v oh v ol t f t f t plh t phl do 1-3 rx 1-3 figure 2. switching characteristics drivers t slh tx 1-3 3v 3v 3v 3v t shl 3v 3v 3v (3v) or slew rate (sr) = t slh t shl figure 3. slew rate characteristics applications information the mc145406 has been designed to meet the electrical specifications of standards eia-232-d/ccitt v.28 and as such, defines the electrical and physical interface between data communication equipment (dce) and data t erminal equipment (dte). a dce is connected to a dte using a cable that typically carries up to 25 leads, which allow the transfer of timing, data, control, and test signals. the mc145406 provides the necessary level shifting between the ttl/cmos logic levels and the high voltage levels of eia-232-d (ranging from + 3 to + 25v). drivers as defined by the specification, an eia-232-d driver presents a voltage of between + 5 to + 15v into a load of between 3 to 7k w . a logic one at the driver input results in a voltage of between -5 to -15v . a logic zero results in a voltage between + 5 to + 15v. when operating at + 7 to + 12v , the mc145406 meets this requirement. when operating at + 5v , the mc145406 drivers produce less than + 5v at the output (when terminated), which does not meet the eia-232-d specification. however, the output voltages when using a + 5v power supply are high enough (around + 4v) to permit proper reception by an eia-232-d receiver , and can be used in applications where strict compliance to eia-232-d is not required. another requirement of the mc145406 drivers is that they withstand a short to another driver in the eia-232-d cable. the worst-case condition that is permitted by eia-232-d is a + 15v source that is current limited to 500ma. the mc145406 drivers can withstand this condition momentarily. in most short circuit conditions the source driver will have a series 300 w output impedance needed to satisfy the eia-232-d driver requirements. this will reduce the short circuit current to under 40ma which is an acceptable level for the mc145406 to withstand. unlike some other drivers, the mc145406 drivers feature an internally-limited output slew rate that does not exceed 30v/ m s. receivers the job of an eia-232-d receiver is to level-shift voltages in the range of -25 to +25v down to ttl/cmos logic levels (0 to +5v). a voltage of between -3 and -25v on rx 1 is defined as a mark and produces a logic one at do 1 . a voltage between +3 and +25v is a space and produces a logic zero. while receiving these signals, the rx inputs must present a resistance between 3 and 7k w . nominally, the input resistance of the rx 1-3 inputs is 5.0k w . the input threshold of the rx 1-3 inputs is typically biased at 1.8v above ground (gnd) with typically 800mv of hysteresis included to improve noise immunity . the 1.8v bias forces the appropriate do pin to a logic one when its rx input is open or grounded as called for in eia-232-d specification. notice that ttl logic levels can be applied to the rx inputs in lieu of normal eia-232-d signal levels. this might be helpful in situations where access to the modem or computer through the eia-232-d connector is necessary with ttl devices. however , it is important not to connect the eia-232-d outputs (tx 1 ) to ttl inputs since ttl operates off +5v only, and may be damaged by the high output voltage of the mc145406. the do outputs are to be connected to a ttl or cmos input (such as an input to a modem chip). these outputs will swing from v cc to ground, allowing the designer to operate the do and di pins from the digital power supply . the tx and rx sections are independently powered by v dd and v ss so that one may run logic at +5v and the eia-232-d signals at + 12v.
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